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AN1046/0199 1/32 application note st7 uart emulation software by microcontroller division application team 1 introduction all members of the stmicroelectronics st7 series of microcontrollers feature a 16 bit timer with several possibilities such as output compares and input captures. this note describes a technique for emulating an rs232 uart with the st7 timer without any additional hardware. only two pins are required for the serial communication. the first part of this note will explain the protocol used for serial communication and how to adapt it for the st7 timer. the other sections of this note describe more precisely how the pro- gram deals with transmitter mode and receiver mode. timings are used to illustrate the important points. the user can easily adapt the example to his own application as only a small amount of code is required by the uart program. the software was tested by connecting a st72251 to the serial port of a pc and communi- cating in all possible modes. 2 uart communications protocol an uart is a two-way communications interface (universal asynchronous receiver trans- mitter). a hardware uart is made of two cells and can work in full duplex mode (transmitter and receiver together). the software module developed below supports full duplex functionality. however, it can be configured in transmitter mode only or receiver mode only. this application note briefly explains the uart protocol and how to configure the module for operation. 1
st7 uart emulation software 2/32 protocol : 1 start bit corresponding to the beginning of the frame. 7 or 8 bits of data corresponding to the data to receive or transmit. 1 stop bit corresponding to the end of the frame. 3 baud rate the baud rate is used to configure the transfer speed. for a hardware cell, the transfer speed is an input clock ratio formed by a pre-defined divider. for the software module, we will use the timer to generate the different speeds, using both the internal clock and the timer clock divider. a pulse period can be calculated using the following formula: example: if a 16 mhz crystal is used, the corresponding period is 62.5 ns but, as a clock divider is im- plemented within the st7, the real period is 125 ns. when using the timer, a prescaler is used and can be configured in the timer control register 2 (bits c0 and c1). to sum up: clock in = 16 mhz 1/16 mhz = 62.5 ns 62.5 ns x 2 = 125 ns st7 core internal clock (f cpu ) 125 ns x 4 = 0.5 s timer prescaler divider the pulse period on the line will be 0.5 s long. so, if a 1200 baud rate is required for the application, the input value you will have to configure in the program will be: 1/1200 = 833 s = 1666 x 0.5 s or 682 hex. start data stop vr02135b 1
3/32 st7 uart emulation software in the software, two 8-bit registers (sh and sl) contain the speed value: sh = 06 h sl = 82 h again, in receiver mode, a half period is required to sample each data, so the next parameter you'll have to provide to the uart program is the half speed, coded over two 8-bit registers (hsh and hsl): 833 / 2 = 416 s = 833 x 0.5 s or 341 hex and hsh=03h hsl=41h lsb msb data stop vr02135c start 833 s 416 s samples used in receiver mode only vr02135d 1
st7 uart emulation software 4/32 standard transfer speed supported : 6 standard speeds are supported by the uart program. a simple calculation based on the previous one allows you to configure the program for each required speed. you can also check the constant.asm file which contains the hex value for each of the following baud rates. 1200 baud 2400 baud 4800 baud 9600 baud 19200 baud 28800 baud refer to the last chapter of this application note for more details on supported speeds. 4 transmitter mode according to the previous calculation, each bit is transmitted on the line with the same dura- tion. but, care must be taken about the protocol used here. instead of starting a communication with a start bit, when the uart function is called within the main program, we first generate a stop condition and, after the stop bit length, we gen- erate the start bit. this way of proceeding insures that a correct start condition will be generated on the line what- ever the previous pin level. so, the frame looks like this, with lsbs sent first : donnes stop start lsb msb time vr02135e 1
5/32 st7 uart emulation software 5 receiver mode receiver mode is more complicated than transmitter mode because of potential errors or noise created by the connections and wiring. so, a simple sampling function cannot ensure a proper bit decision. a 2 to 1 majority voting system is used to determine the bit level on the line. three samples are taken on the line at mid period and a decision is taken based on the sampling process. a falling edge followed by a low level on the receive pin will start the process while a one level after the 9 first bits stands for a stop condition. so, if a glitch occurs on the line, generating a falling edge detection, it won't be considered as a start bit unless it is followed by a low level for a bit duration. principle : once the uart routine is called and when it is configured in receiver mode only, the input pin waits for a falling edge. once an edge is detected, an interrupt is generated and the half dura- tion of the bit (hsl and hsh registers) is loaded in the timer output compare registers (oclr and ochr). when the output compare interrupt occurs, the sampling process is done and a low level must be detected on the line (it's a start bit). if not, a flag is set meaning that the frame is incorrect and the software stops. but if yes, a full bit duration is added to the output compare value of the timer so that the same sampling process will be executed in the middle of the first data bit. after all eight data bits have been received, the uart program tests if the bit received is at a high level for the stop bit. once again, if not, the same flag (frame error) is used to warn that the frame is not good. a flag indicates when the transmission is over and the data received is located in a ram reg- ister. data stop start sampling vr02135g 1
st7 uart emulation software 6/32 examples: 1. for a data bit: if two samples out of the three are "0" then the data is a 0 but, as one of the sample was a 1, the noise frame flag in the status register is set. 2. for the start bit: two samples out of the three taken must be zeros. if not, the frame error flag is set in the status register and the frame is incorrect. 3. for the stop bit: two samples out of the three taken must be ones. if not, the frame error flag is set in the status register and the frame is incorrect. 6 functional description the uart is controlled through 6 registers. we've already seen 4 of them, sh, sl, hsl and hsh for the transmission speed and the two others are scsr and sccr2, respectively for status register and for control register. control register sccr2 : the register is described below: bit 0 => 7/8 if this bit is set, the transmission or the reception is 7 bits long. bit 1 => sev if this bit is set, another byte will be transmitted on the line. care must be taken when you decide to set this bit, refer to the timing explanation later in this document. bit 2 => rx if this bit is set, the receiver function is enabled. bit 3 => tx if this bit is set, the transmitter function is enabled. bit 4 => ready this bit is read only. when set, it indicates that the uart can accept another byte. refer to the timing explanation further in this document. bit 5 to 7 unused. notes : 1) the reset value of this register is 00h. 2) when te = 1 and re=1, full duplex mode is enabled and the transfer throughput cannot ex- ceed 9600 baud. sccr2 7/8 rx tx b0 b7 ready vr02135h 1
7/32 st7 uart emulation software status register bit 0 => x unused bit 1 => fe frame error: when set, this bit indicates that the reception is incorrect (start bit or stop bit invalid). bit 2 => nf noise frame: when set, this bit indicates that some noise interfered on the line but that the result is still coherent. bit 3 and 4 => x unused. bit 5 => rdrf receive data register full: when set, this flag indicates that all the bits of the data register are received. bit 6 => tc transmit complete: when set, this flag indicates that a whole frame has been sent, including the stop bit and the start bit. bit 7 => x unused the fe and nf flags are used to control the result of the communication. the rdrf flag is used to control receiver mode (when set, the data can be read in the received data register). the tc flag is used to control transmitter mode (when set, the data has been sent on the line). data registers : the uart has three data registers: scdat_emit for the data that have been transmitted on the tx line. scdat_rec for the data that have been received on the rx line. newdata for the next byte to be transmitted on the tx line. fe nf b0 b7 rdrf tc scsr xx xx vr02135i 1
st7 uart emulation software 8/32 particular timings for sev and ready flags : in transmitter mode, the uart might have to send more than one byte. the two flags ready and sev (for several) in the sccr2 register are used to handle a hand- shake protocol. when the uart is sending bits on the tx line, a shift register is used to serialise the data stream. however, the user must indicate to the uart if there's another byte to send after- wards. the timings are: between bit 1 and bit 9, the uart can accept another byte (ready = 1) at any time. if the user wants to send a byte, he has to load the data in the newdata register and set the sev bit. when bit 9 is being transferred on the line, the uart indicates that it cannot accept another byte (ready = 0) and tests the sev flag. if set, then the content of newdata will be loaded in the scdat_emit register for the next transfer. the uart resets the sev bit and puts ready to high meaning that the user can send another byte if necessary. if reset, a stop is generated and further transmission can be achieved only by calling the uart routine again. the 10th bit will be followed by a stop and a start bit and after this, the byte will be trans- ferred on the tx line. lsb msb 12345678910 bit n : ready sev user wants to send a data (ready line was at high level) 9th bit: the ready line goes low for more than one bit period. (test if sev bit = 1) the uart cell the new data to send is latched in the uart resets the sev bit and put the ready line high. vr02135j 1
9/32 st7 uart emulation software 7 hardware description the routine runs on the st72251 microcontroller and uses one 16-bit timer. three timer func- tions are used: the two output compares and the input capture 1 of timer a. - 2 lines are used for tx and rx. tx is the output compare pin 1 of timer a (pb1) and rx is the input capture pin 2 of timer a (pb2). note : the routine uses all resources of timer a. for correct handling, it's better not to use timer a for other tasks if you can use timer b instead. 8 software description to use the uart program, follow this procedure: n configure the speed registers in the constant.asm file according to the chosen mode. n configure the sccr2 register to indicate which mode is enabled (transmitter only, receiver only, full duplex). n configure the pb1 pin in order to put pb1 at high level and reset the olv1 bit of the tacr1 register (see main asm program for precise details). n load the data to transmit in the newdata register, if transmitter mode is chosen. n and finally, make the call uart this is all you have to do in order to use the uart. the following chapter explains how the uart works but if you wish, you can skip this chapter and go directly to the example given at the end of this document. microcontroller st7225 port b2 port b1 tx rx vr02135k 1
st7 uart emulation software 10/32 transmitter mode: the first step in transmitter mode, is to initialise the pb1 pin to a high level. however, a simple bit set (bset instruction) doesn't ensure a proper level on the pin. as we are using the alternate function of the pb1 pin, the bset instruction will turn the i/o mode on but will not change the pin level properly. to initialise it correctly, an output compare with olvl1 = 1 must first be done. by polling the ocf1 flag of timer a status register (tasr) you can verify that the pin is cor- rectly set and the rest of the program can continue. the second step of transmitter mode is to set the te flag in the sccr2 register and then to program the uart. when the call uart has been done, the routine reads the alternate counter value and adds the bit period depending on the transmission speed and loads the calculated value in the output compare 1 registers. olvl1 is reset in order to generate the start bit (remember that the sequence is stop, start, data...). the main program can resume as the uart rou- tine is, for now, over. when the counter reaches the output compare value, a low level is applied on the line (olvl1=0), the interrupt routine loads a new value (old output compare value + bit period) in the output compare registers and, the olvl1 bit is set or reset depending on the first data bit (data bits are shifted serially in the carry). when a frame has been transmitted, the tc flag is set and you can send another frame. 1
11/32 st7 uart emulation software the following timing represents a full transmission. "call uart" set ready reset sev if necessary it lsb msb 12345678910 0 first it: olvl1 copied to pb1 uart initialization, pb1 pin = 1 with a first output compare. olv1=0 for the next output compare (= start bit). 0: 1: stop bit, 2: start bit. during the interrupt routine, the output compare registers are loaded with the next output compare value and olv1 is configured according to the lsb value. second it it it it it it reset ready flag test if there is another byte to send this last it is generated only if there is another byte to send, else no it is generated and the line is left high. time i t it vr02135l 1
st7 uart emulation software 12/32 notes : C between two interrupts, the main program is free for other tasks. the uart program works with interrupts only. C all interrupts are output compare 1 interrupts (ocf1 flag). C interrupts coming from other devices will not disturb operations provided they are shorter than a bit duration minus the uart it length, i.e provided that the interrupt length fits be- tween two interrupts from the uart. receiver running mode: once the uart has been configured in receiver mode, the software waits for a fa lling edge on the pb2 pin which represents the start bit. to detect the falling edge, the input capture interrupt is turned on and the first interrupt routine is executed. as soon as the falling edge is detected, the input capture routine disables the input capture in- terrupt on the pin (a high to low transition between two data bits must not be seen as a start bit!) and the half bit duration is added to the alternate counter value to load the output compare 2 registers. once the first output compare 2 interrupt occurs, we are in the middle of the start bit, and the sampling process starts. if everything went right (2 or 3 samples at 0), the routine adds a full bit duration to the old output compare value and loads it in the output compare registers. call uart ready sev tc tx only one byte is sent, so tc is set, otherwise, it stays low until last byte is reached. vr02135m 1
13/32 st7 uart emulation software the next output compare 2 interrupt will occur in the middle of the first data bit, the sampling process will tell which level was received (0 or 1). the process continues until the stop bit detection. the last interrupt triggers the input capture interrupt on the pb2 pin in order to detect the next start bit. -at the end of the reception, the rdrf flag is set. the following timing represents a full reception: notes: C between two interrupts, the main program is free for other tasks. the uart works with in- terrupts only. C interrupts coming from other peripherals (or external pins) should be disabled so as not to disturb the sampling process. note concerning full duplex mode: although receiver and transmitter mode can run at 19200 baud, full duplex mode is slower due to the interrupt routine length. in fact, each routine has its own execution time and if another in- terrupt occurs at this moment it cannot be served. lsb msb "call uart" 123456789 it it it it time input capture interrupt it it it it it input capture interrupt turned on. input capture interrupt turned off. it output compare 2 interrupts 1 0 vr02135n 1
st7 uart emulation software 14/32 the following table gives the precise length of each routine. for example, the following is an example using the information given in the table: if you are in receiver mode, the worst case you can encounter is when you are in the middle of the frame. between the time you get the output compare 2 interrupt and when you exit the subroutine there are 177 cpu cycles. so, this means that, if a cpu cycle is 125 ns long, the fastest transmission you can accept is: 177 x 125 ns = 22,125 s between two data bits. consequently: 28800 baud <=> 34,72 s 19200 baud <=> 52.08 s are both possible transmission rates. in full duplex mode, two consecutive worst cases must be taken into account. so the worst case that could occur is 177 + 94 = 271 cpu cycles = 33,875 s the closest standard speed to this worst case is: 19200 baud <=> 52.08 s 9600 baud <=> 104,17 s which are both possible transmission rates. from to receiver full du- plex trans- mitter worst case call uart ret in- struction 68 cpu cycles 236 cpu cycles 174 cpu cycles word = 8 bits icap2 interrupt iret in- struction 78 cpu cycles xxx output compare 2 interrupt iret in- struction 177 cpu cycles xx data processing, no special case (start or stop bit) output compare 1 interrupt iret in- struction x x 94 cpu cycles normal data processing 1
15/32 st7 uart emulation software the total number of bytes for the routine is: 393 bytes of rom + 37 more bytes for the pb1 pin initialisation in the main program and 18 bytes in the ram memory space for internal varia- bles. 9 communication with a pc the st7 emulated uart cannot be directly connected to a pc, as it uses the rs232 protocol. the electrical and protocol characteristics of rs232 are different from those provided by the timer i/o pins. in rs232 communication, the high level is typically +7v and the low level is typically -7v, while the timer peripheral works at ttl levels (0, +5v). furthermore, the polarities are different. a 1 bit coming from the timer corresponds to a 0 bit in rs232, and a 0 bit to a 1 bit. this is true for all bits including the start and stop bits . so it is necessary to implement a conversion between the pc and the st7. in the application, a max232 is used for this purpose. an overview schematic is presented below (figure 1.). figure 1. overview schematic be sure that the three main devices (pc, st7, max232) have the same electrical reference (gnd). the receive data pin (rd) of the serial port of the pc must correspond to the ocmp1 pin of the st7, and the transmit data pin (td) to the icap1 pin. note for the main program example: when using the uart in full duplex mode, there's no time left in the main program for other tasks. you must disable all other interrupt sources in order to make a correct full duplex trans- mission. in transmitter mode, the following flowchart is given as an example for handling the different flags (tc, ready, sev). pc terminal serial port td rd ground max232 in out out in st72251 gnd gnd gnd icap1 pin ocmp1 pin 1
st7 uart emulation software 16/32 an upper level subroutine called "send_data" has been written. use it in your main program if you want to send a data with the uart program. to conclude, a transmission example is shown illustrating all cases with different states of the sev and ready bits. call send_byte data to send ? test if sev = 1 ? test if ready = 0 ? ret ret load newdata load newdata sev = 1 ret ret call uart n n y y y n resynchronisation process vr02135o
17/32 st7 uart emulation software sev bit sev bit ready bit tx line tx line ready bit p s data p s data p s data p s data test test test call send_data call send_data call send_data call send_data call send_data test call send_data resynchronisation : both lines are low ! call uart ! p: stop bit s: start bit no write allowed both lines are high no write allowed both lines are high sev bit = 0 so it means that the users forgot to put it at 1. the ready bit goes low because of the desynchronisation vr02135a
st7 uart emulation software 18/32 10 software the assembly code given below is guidance only. the file cannot be used alone. the com- plete software can be found in the st.com website. st7/ ;************************************************************************ ; title: uart.asm ; author: microcontroller division applications team ; description: main program ;************************************************************************ title uart.asm ;************************************************************************ ; | ; this program performs a software u a r t in transmitter or receiver modes | ; (<=> half duplex uart)and also a full duplex mode for fast data exchange | ; | ;************************************************************************ ; start bits falling edge detected with the timers input capture function. ; | ; | ; | start <------------------ data ---------------------> stop ; | | | ; | ----| |-----|-----|-----|-----|-----|-----|-----|-----|-----|--------- ; |---->| | b0 b1 b2 b3 b4 b5 b6 b7 | ; |_____|-----|-----|-----|-----|-----|-----|-----|-----| ; ; samples ||| ||| ||| ||| ||| ||| ||| ||| ||| ||| ; | ; (only in receiver mode) ; the uart is controlled by two registers (sccr2 and scsr) and has three ; data registers (scdat_rec, scdat_emit and newdata). ; the two control registers are described below while scdat_rec is the ; data register for incoming bytes, scdat_emit is the data register for outgoing ; byte and newdata is the data register which holds the next value to transfert.
19/32 st7 uart emulation software ; sccr2: control register ; ; ------------------------ ; |x|x|x|rd|tx|rx|sev|7/8| ; ------------------------ ; ---- | | | | | ; | | | | | | ; unused | | | | frame length: 1= 7 data bits in byte, 0= 8 data bits. ; | | | several bytes: if you want to send another byte after the ; | | | one which is being transfered. ; | | receive function turned on if set. ; | transmit function turned on if set. ; ready flag: when set, the uart can accept another byte ; scsr: status register ; ; ------------------------------ ; |tdre|tc|rdrf|x|x|nf|fe|start| ; ------------------------------ ; | | | | | |-> start_bit : when set, the uart must generate a start bit ; | | | | frame error. when set, the frame is not valid ; | | | noise frame. the flag is set when 1 of the three samples ; | | | taken in the frame is different from the two others. ; | | receive data register full: when the byte is received the flag is set. ; | transmit completed: end of frame (with the stop bit) ; transmit data register empty: data register empty. ; ;--------------------------------------------------------------------------- #include st72251.inc ; insert register definition of the st72251 #include constant.inc ;*************************************************************************** * ; user program ;************************************************************************** words segment rom ;--------------------------------------------------------------------------- ; user software ;--------------------------------------------------------------------------- .main ld a,#$08 ; negative edge only ld miscr,a ; normal mode
st7 uart emulation software 20/32 ld x,#$80 .raz clr (x) ; clear 62 bytes in ram inc x ; for full duplex mode cp x,#$ff ; (to copy received data into ram). jrne raz ; disable the timer interrupts ld a,tasr ; clear status flags clr taoc1lr clr taoc2lr rim ; it output compare will be enabled when oclr is clr taoc1hr ; written. clr taoc2hr ; stop timer output compare 1 and 2 ; init pb1 pin ld a,#$80 ; put the output compare pin 1 on ld tacr2,a ; clock ratio = 4 <=> one bit = 1s ld a,#$01 ld tacr1,a ; olvl1=1 and no output compare interrupt ld a,taachr ; read alternate counter (high byte) ld sochr,a ; save value of high register ld a,taaclr ; read alternate counter register (low byte) add a,#80 ; add 80 cycles to the current value ld soclr,a ; to generate a first output compare ld a,sochr ; in order to set the alternate level to one. adc a,#00 ld sochr,a ; further compare inhibited ld taoc1hr,a ld a,tasr ; clear flag of timer1 ld a,soclr ld taoc1lr,a ; start output compare .pb1_init btjf tasr,#6,pb1_init ; wait for the output compare flag ld taoc1hr,a ; further compare inhibited ; the compare1 function will be restored ; if transmission mode is selected. ; uart initialisation loopa clr y clr x ld a,#$21 ld newdata,a ;first character to send (!) bset sccr2,#re ; receive mode selected bset sccr2,#te ; transmit mode selected call uart
21/32 st7 uart emulation software ; ************************************************************ ; if you want to test the receiver function of the uart program, remove ; the comma to jump to the read loop; (re bit=1 and te=0) ; jp loop_read ; ************************************************************ ; ************************************************************ ; if you want to test the full duplex function of uart program, remove ; the comma to jump to the duplex loop; (re bit=1 and te=1) jp loop_duplex ; ******************************************************************* ;***************************************************************** ; sending of several independent characters to test the transmission ; function of uart program; (re bit=0 and te=1) ;***************************************************************** loop5 btjf sccr2,#ready,loop5 ;wait for the ready flag bset sccr2,#1 ; once the flag is set, set flag for another byte ld a,#j ; and load register ld newdata,a loop7 btjt sccr2,#ready,loop7 ; wait for the ready flag to go down loop6 btjf sccr2,#ready,loop6 ; wait for the ready flag to go up bset sccr2,#1 ; once the flag is set, set flag for another byte ld a,#- ; and load register ld newdata,a loop11 btjt sccr2,#ready,loop11 ; wait for the ready flag to go down loop9 btjf sccr2,#ready,loop9 ; wait for the ready flag to go up bset sccr2,#1 ; once the flag is set, set flag for another byte ld a,#s ; and load register ld newdata,a loop12 btjt sccr2,#ready,loop12 ; wait for the ready flag to go down loop10 btjf sccr2,#ready,loop10 ; wait for the ready flag to go up bset sccr2,#1 ; once the flag is set, set flag for another byte ld a,#$32 ; and load register ld newdata,a loop8 btjt sccr2,#ready,loop8 ; wait for the ready flag to go down bres sccr2,#1 ; no other byte loop2 btjf scsr,#tc,loop2 ; wait for transmition complete flag loop jra loop
st7 uart emulation software 22/32 ;******************************************************************** ; if you want to test the transmission function of uart program and ; send more than one byte with the uart, you can still ; use this example of main program. an entire name is sent (applications). ;******************************************************************** example ld x,#11 begin ld a,(first_name,x) ; load first character to send ld newdata,a call uart lp btjf scsr,#tc,lp bres scsr,#tc ; clear tc flag dec x tnz x jreq over jra begin over ld a,(first_name,x) ; sending of the last character ld newdata,a call uart lp2 btjf scsr,#tc,lp2 bres scsr,#tc ; clear tc flag ;***************************************************************** ;***************************************************************** .loop_duplex btjt sccr2,#ready,load_data ; wait for the ready flag btjt sccr2,#1,res_flag ; ready=0 and sev=1 -> reset sev flag polling btjt scsr,#rdrf,read_data ; wait for the end of reception flag btjt scsr,#tc,end_transmit ; wait for the transmition complete flag jra loop_duplex res_flag bres sccr2,#1 ; instructions executed only when ready=0 jra polling ; and sev=1 load_data btjt sccr2,#1,exit ; test if sev = 1. if so, wait for ready to go down bset sccr2,#1 ; else, set flag for an other byte ld a,taaclr ; and load register with counters low byte ld newdata,a ; for a random value jrpl end_transmit
23/32 st7 uart emulation software exit jra polling .end_transmit bres scsr,#tc ; clear flag jra polling .read_data inc x ld a,scdat_rec ; store data in ram ld (scdat_rec,x),a bres scsr,#rdrf ; clear frame received flag jra polling ;***************************************************************** ;***************************************************************** ; the read loop shows how to receive three bytes from a master device. ;***************************************************************** loop_read read1 btjf scsr,#rdrf,read1 ; wait for the end of reception flag ld a,scdat_rec ld {scdat_rec+1},a clr scsr ; read data and clear flag read2 btjf scsr,#rdrf,read2 ; wait for the end of reception flag ld a,scdat_rec ld {scdat_rec+2},a clr scsr ; read data and clear flag read3 btjf scsr,#rdrf,read3 ; wait for the end of reception flag ld a,scdat_rec ld {scdat_rec+3},a bset sccr2,#ready .loopr jra loopr ;*************************************************************************** ; u a r t subroutine ;*************************************************************************** .uart btjt sccr2,#seven,seven_bits ; test the transmissions length ld a,#{8+2} ; the words length is eight bits jra c_status .seven_bits ld a,#{7+2} ; the words length is seven bits
st7 uart emulation software 24/32 .c_status bres sccr2,#1 ; reset sev bit for main program bset sccr2,#ready ; set ready bit for main program ld cpt_bit_emit,a ld cpt_bit_rec,a ld nb_bit_emit,a ld nb_bit_rec,a ld a,newdata ; get the new value to transfer ld scdat_emit,a ; in the transmitters data register clr scsr ; clear all flags btjt sccr2,#re,receiver ; check if receiver was requested .transmiter_only ; no, then half duplex transmitter only ; no receiver function requested (= transmitter function) ; in transmitter mode, the real sequence is: ; ; |stop|start|data7|data6|...|data0| ; ; rather then ; ; |start|data7|data6|...|data0|stop| ; ; so the next two decrementations stand for the stop bit. dec nb_bit_emit dec cpt_bit_emit ; timer initialization bset tacr1,#6 ; enable the output compare interrupts bres tacr1,#0 ; reset olv1 for the start bit ld a,taachr ; read the current free running counter value ld sochr,a ; save value of high register ld a,taaclr add a,#sl ; add the bit duration and save the value ld soclr,a ld a,sochr adc a,#sh ld sochr,a ; further compare inhibited ld taoc1hr,a ; load added value to the output compare 1 registers ld a,tasr ; clear flag of timer1 ld a,soclr ld taoc1lr,a ; and start the output compare function ret
25/32 st7 uart emulation software .receiver dec nb_bit_rec ld a,#$c0 ; input capture and output compare interrupts ld tacr1,a ; enabled. bres tacr2,#1 ; input capture edge sensitivity = falling edge ; test if we are in full_duplex mode btjt sccr2,#te,transmiter_only ret ;--------------------------------------------------------------------------- ; timer a interrupt routine ;--------------------------------------------------------------------------- ; check which mode generated the timer a interrupt: ; output compare1 (transmission mode) ; output compare2 (reception mode) ; input capture (reception mode) .tima_rt btjf tacr1,#7,continue ; test if the input capt interrupt is enabled btjt tasr,#4,start_reception; flag=1 so test input capture 2 flag .continue ; else icfe flag is reseted or its not the right ; edge on icap2 btjt tasr,#6,trans ; so test output compare 1 flag ; else output compare 2 flag btjt tasr,#3,temp ; jump to the receiver function iret .temp jp recept ; re = 0 so transmit mode is selected .trans btjt scsr,#start_bit,restart ; test if start flag is set btjt scsr,#tdre,arret ; if tdre is set transmission completed ; so stop the timer ld a,cpt_bit_emit ; test which bit is sending on the line cp a,#1 ; test if there is only one bit left in the jreq last_bit ; data register bset sccr2,#ready ; uart can accept another byte .send sra scdat_emit ; shift the bits of the data register into jrc one ; the carry. lsb first bres tacr1,#0 ; change olvl1 to 0 for the next compare jra fin
st7 uart emulation software 26/32 .one bset tacr1,#0 ; change olvl1 to 1 for the next compare ; load the new timer value ; new output compare value = old output compare value + bit length value .fin dec cpt_bit_emit .fin1 ld a,soclr ; add the duration value into save register add a,#sl ld soclr,a ld a,sochr adc a,#sh ld sochr,a ; further compare inhibited ld taoc1hr,a ld a,tasr ; clear flag of timer1 ld a,soclr ld taoc1lr,a ; start output compare iret .last_bit bres sccr2,#ready ; uart may read the newdata register btjt sccr2,#1,one_more ; test if theres another byte to transfer bset scsr,#tdre ; no, so the data transmission register has been sent. bset tacr1,#0 ; set olv1 to keep line at high level (stop bit). jp fin .one_more bset tacr1,#0 ; olvl1 = 1 for the stop bit bset scsr,#start_bit ; one more byte, so set start bit jp fin ; another byte must be transfered .restart bres tacr1,#0 ; olvl1 = 0 for the start bit ld a,nb_bit_emit ; get frame length ld cpt_bit_emit,a ; reset cpt_bit with frame length bres scsr,#start_bit ; clear start bit ld a,newdata ld scdat_emit,a ; get new byte to send bset sccr2,#ready ; set ready bit for main program bres sccr2,#1 ; reset sev bit to inform the main program ; that the new data had been latched. jp fin1 ; and wait for one period. .arret ; stop output compare
27/32 st7 uart emulation software ld a,tasr clr taoc1lr clr taoc1hr bset scsr,#tc ; the frame has been sent. iret ;--------------------------------------------------------------------------- ; receive mode: | ; y register is incremented when a high level is detected on rx line | ; x register is incremented when a low level is detected on rx line | ;--------------------------------------------------------------------------- ; input capture condition .start_reception ld a,taic2hr ; read the input capture value ld sochr2,a ; msb first and store value ld a,taic2lr ld soclr2,a add a,#hsl ; add the half duration value into save register ld soclr2,a ld a,sochr2 adc a,#hsh ld sochr2,a ; further compare inhibited ld taoc2hr,a ld a,tasr ; clear timers flag bres tacr1,#7 ; disable input capture interrupt ld a,nb_bit_rec ; get frame length inc a ld cpt_bit_rec,a ld a,soclr2 ld taoc2lr,a ; start output compare iret ; and wait for output compare2 interrupt ; test the stop bit condition on the line .stop0 clr x btjt pbdr,#rx,st10 ; check 1st sample bset scsr,#nf jp st100 .st10 inc x .st100 btjt pbdr,#rx,st11 ; check 2nd sample bset scsr,#nf ; noise detected
st7 uart emulation software 28/32 jp st101 .st11 inc x .st101 btjt pbdr,#rx,st12 ; check 3rd sample bset scsr,#nf ; noise detected jp st113 .st12 inc x .st113 cp x,#2 jrc f_error jp t_received f_error bset scsr,#fe ; if a majority of samples are 0 jp t_received ; then its an error. .recept push x ; save users registers push y dec cpt_bit_rec ; test if we are receiving the last bit ld a,cpt_bit_rec jreq stop0 ; if so, then test only 1 samples cp a,nb_bit_rec ; else, test if we are receiving the start bit jreq start0 ; and if so , test only 0 samples ; if none of the above, we are receiving data bits ; ; process data sample ; clr y clr x btjt pbdr,#rx,t10 ; check 1st sample inc x ; sample = 0 so increment x jrnc t20 .t10 inc y ; sample = 1 so increment y .t20 btjt pbdr,#rx,t30 ; check 2nd sample inc x jrnc t40 .t30 inc y ; second sample = 1 so increment y .t40 btjt pbdr,#rx,t50 ; check 3rd sample inc x jrnc t60 .t50 inc y .t60 cp y,#3 ; if y= 3 and x = 0 a sample 1 jrne t61 ; has been detected three times jp decal ; sample 1 into the scdat register .t61 cp x,#3 ; if x= 3 and y= 0 a sample 0
29/32 st7 uart emulation software jreq t63 ; has been detected three times bset scsr,#nf .t62 ld nbr_b1,y ld a,x cp a,nbr_b1 ; compare x and y to determine jrc decal ; the value of the bit received .t63 rcf ; reset carry jp decal11 .decal scf ; set carry .decal11 rrc scdat_rec ; shift carry into the data register jp fin0 ; 1st bit received = lsb ; test the start bit condition on the line .start0 clr x btjf pbdr,#rx,s0 ; check 1st sample bset scsr,#nf jp s00 .s0 inc x .s00 btjf pbdr,#rx,s01 ; check 2nd sample bset scsr,#nf ; noise detected jp s002 .s01 inc x .s002 btjf pbdr,#rx,s02 ; check 3rd sample bset scsr,#nf ; noise detected jp s003 .s02 inc x .s003 cp x,#2 jrnc fin0 ; if the majority of the samples are 1 bset scsr,#fe ; its an error. pop y ; restore users registers pop x ; and quit uarts routine iret ; load the new timer value .fin0 ld a,soclr2 ; add the duration value into save register add a,#sl ld soclr2,a ld a,sochr2 adc a,#sh ld sochr2,a ; further compare inhibited
st7 uart emulation software 30/32 ld taoc2hr,a ld a,tasr ; clear flag of timer1 ld a,soclr2 ld taoc2lr,a ; start output compare pop y ; restore users registers pop x iret .t_received bset scsr,#rdrf ; the frame has been sent. ; stop output compare ld a,tasr ; clear interrupt flags clr taic2lr ; clear input capture flag clr taoc2lr clr taoc2hr ; disable output compare ld a,#$c0 ; input capture and output compare interrupts ld tacr1,a ; enabled. bres tacr2,#1 ; input capture edge sensitivity = falling edge pop y ; restore users registers pop x iret ; ******************************************** ; * * ; * interrupt sub-routines library section * ; * * ; ******************************************** dummy iret ext1_rt iret ext0_rt iret sw_rt iret spi_rt iret timb_rt iret i2c_rt iret
31/32 st7 uart emulation software ;*************************************************************************** ; interrupt and restart vectors * ;*************************************************************************** segment vectit dc.w not used ;ffe0-ffe1h location dc.w not used ;ffe2-ffe3h location .i2c_it dc.w dummy_rt ;ffe4-ffe5h location dc.w not used ;ffe6-ffe7h location dc.w not used ;ffe8-ffe9h location dc.w not used ;ffea-ffebh location dc.w not used ;ffec-ffedh location .timb_it dc.w dummy_rt ;ffee-ffefh location dc.w not used ;fff0-fff1h location .tima_it dc.w tima_rt ;fff2-fff3h location .spi_rt dc.w dummy_rt ;fff4-fff5h location dc.w not used ;fff6-fff7h location .ext1_it dc.w dummy_rt ;fff8-fff9h location .ext0_it dc.w dummy_rt ;fffa-fffbh location .softit dc.w dummy_rt ;fffc-fffdh location .reset dc.w main ;fffe-ffffh location ; this last line refers to the first line. ; it used by the compiler/linker to determine code zone end ; be aware that the end directive should not ; stand on the left of the page like the label names.
st7 uart emulation software 32/32 the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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